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Part: AM28F512A-200FIB
Category:
Description: 512 Kilobit CMOS 12.0 Volt, Bulk Erase Flash Memory With Embedded Algorithms
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM28F512A-200FIB datasheet File size : 427 kB
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FINAL
Am28F512
512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s High performance -- 70 ns maximum access time s CMOS Low power consumption -- 30 mA maximum active current -- 100 µA maximum standby current -- No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts -- 32-pin PDIP -- 32-pin PLCC -- 32-pin TSOP s 10,000 write/erase cycles minimum s Write and erase voltage 12.0 V ±5% s Latch-up protected to 100 mA from -1 V to VCC +1 V s Flasherase Electrical Bulk Chip-Erase -- One second typical chip-erase s Flashrite Programming -- 10 µs typical byte-program -- One second typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology -- Low cost single transistor memory cell s Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
T he Am28F512 is a 512 K bit Flash memory organized as 64 Kbytes of 8 bits each. AMD's Flash memor ies offer the most cost-effective and reliable read/ w r i t e non-volatile random access memor y. The A m 28F 51 2 is packaged in 32-pin PDIP, PLCC, and T SO P versions. It is designed to be reprogrammed a n d erased in-system or in standard EPROM programm ers. The Am28F512 is erased when shipped from the factory. The standard Am28F512 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F512 has separate chip enable (CE#) and output enable (OE#) controls. AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F512 uses a command register to manage this f u nc t io n a li ty, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register a llow s for 100% TTL level control inputs and fixed power supply levels during erase and programming. AMD's Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and proPublication# 11561 Rev: G Amendment/+2 Is sue Date: January 1998
gramming mechanisms. In addition, the combination of a dva nce d tunnel oxide processing and low internal electric fields for erase and programming operations p r o d u c e s reliable cycling. The Am28F512 uses a 1 2 . 0 V ± 5 % V P P high voltage input to perform the Flasherase and Flashrite algorithms. The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1 V to VCC +1 V. The Am28F512 is byte programmable using 10 ms programming pulses in accordance with AMD's Flashrite programming algorithm. The typical room temperature pro gramm in g time of the Am28F512 is one second. The entire chip is bulk erased using 10 ms erase pulses according to AMD's Flasherase algorithm. Typical erasure at room temperature is accomplished in less than on e second. The windowed package and the 15-20 minutes required for EPROM erasure using ultra-violet light are eliminated. Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During
write cycles, the command register internally latches add res s and data needed for the programming and erase operations. For system design simplification, the Am28F512 is designed to support either WE# or CE# c on t ro ll ed writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.
A MD's Flash technology combines years of EPROM and EEPROM experience to produce the highest levels o f quality, reliability, and cost effectiveness. The Am28F512 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are prog r a m m e d one byte at a time using the EPROM programming mechanism of hot electron injection.
BLOCK DIAGRAM
DQ0DQ7 VCC VSS VP P Erase Voltage Switch State Control Command Register To Array Input/Output Buffers
W E#
Program Voltage Switch
CE# OE#
Chip Enable Output Enable Logic
Data Latch
Low VCC Detector Program/Erase Pulse Timer A0A15 Address Latch
Y-Decoder
Y-Gating
X-Decoder
524,288 B it Cell Matrix
11561G-1
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V ± 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) -70 70 70 35 -90 90 90 35 Am28F512 -120 120 120 50 -150 150 150 55 -200 200 200 55
2
Am28F512
CONNECTION DIAGRAMS
PDIP PLCC
VPP NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V CC WE# (W#) NC A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7 DQ6 DQ5 DQ4 DQ3
11561G-2
432 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7
14 15 16 17 18 19 20 VSS DQ3 DQ1 DQ2 DQ4 DQ5 DQ6
11561G -3
Note: Pin 1 is marked for orientation.
Am28F512
WE# (W#) NC
VCC
A12 A15
VPP
NC
3
CONNECTION DIAGRAMS (continued)
A11 A9 A8 A13 A14 NC WE# VCC VPP NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin -- Standard Pinout
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC VPP NC A15 A12 A7 A6 A5 A4
11561G-4
32-Pin -- Reverse Pinout
LOGIC SYMBOL
16 A0A15 DQ0DQ7 8
CE# (E#) OE# (G#) WE# (W#)
11561G-5
4
Am28F512
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM28F512 -70 J C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) E = Extended (55°C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am28F512 512 Kilobit (64 K x 8-Bit) CMOS Flash Memory
Valid Combinations AM28F256-70 AM28F256-90 AM28F256-120 AM28F256-150 AM28F256-200 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE
Valid Combinations Valid Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am28F512
5
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