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Part: AM27X128-255JI
Category:
Description: 128 Kilobit ( 16 K X 8-bit ) CMOS Expressrom Device
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM27X128-255JI datasheet File size : 427 kB
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FINAL
Am27X128
128 Kilobit (16 K x 8-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
s As an OTP EPROM alternative: -- Factor y optimized programming -- Fully tested and guaranteed s As a Mask ROM alternative: -- Shor ter leadtime -- Lower volume per code s Fast access time -- 55 ns s Single +5 V power supply s Compatible with JEDEC-approved EPROM pinout s ±10% power supply tolerance s High noise immunity s Low power dissipation -- 100 µA maximum CMOS standby current s Available in Plastic Dual-In-line Package (PDIP) and Plastic Leaded Chip Carrier (PLCC) s Latch-up protected to 100 mA from 1 V to VCC + 1 V s Versatile features for simple interfacing -- Both CMOS and TTL input/output compatibility -- Two line control functions
GENERAL DESCRIPTION
The Am27X128 is a factory programmed and tested OTP EPROM. It is programmed after packaging prior to final test. Every device is rigorously tested under AC and DC operating conditions to your stable code. It is organized as 16 Kwords by 8 bits per word and is available in plastic dual in-line packages (PDIP), as well as plastic leaded chip carrier (PLCC) packages. ExpressROM devices provide a board-ready memory solution for medium to high volume codes with short leadtimes. This offers manufacturers a cost-effective and flexible alter native to OTP EPROMs and mask programmed ROMs. D a t a can be accessed as fast as 55 ns, allowing high-performance microprocessors to operate with reduced WAIT states. The device offers separate Output En able (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. A M D 's CMOS process technology provides high sp ee d , low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 µW in standby mode.
BLOCK DIAGRAM
VC C VSS OE# CE# Output Enable Chip Enable and Prog Logic Y Decoder A0A13 Address Inputs Output Buffers Data Outputs DQ0DQ7
Y Gating
X Decoder
131,072 Bit Cell Matrix
12083F-1
Publication# 12083 Rev: F Amendment/0 Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% -55 55 55 35 -70 70 70 40 -90 90 90 40 -120 120 120 50 -150 150 150 50 -200 200 200 50 250 250 50 Am27X128 -255
Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns)
CONNECTION DIAGRAMS Top View
DI P P L CC
PGM# (P#) A13
A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
2 3 4 5 6 7 8 9 10 11 12 13 14
27 26 25 24 23 22 21 20 19 18 17 16 15
PGM# (P#) A13 A8 A9 A11 OE# (G#) A10 CE # (E#) DQ7 DQ6 DQ5 DQ4 DQ3
12083F-2
4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS DU DQ3 DQ4 DQ1 DQ2 DQ5 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE# (G#) A10 CE# (E#) DQ7 DQ6
VCC
A7 A12
VPP
VPP
1
28
VCC
DU
12083F-3
Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don't use (DU) for PLCC.
PIN DESIGNATIONS
A0A13 CE# (E#) DQ0DQ7 OE# (G#) PGM# (P#) VCC V PP V SS NC = Address Inputs = Chip Enable Input = Data Input/Outputs = Output Enable Input = Program Enable Input
LOGIC SYMBOL
14 A0A13 DQ0DQ7 CE# (E#) 8
= VCC Supply Voltage = Program Voltage Input = G round = No Internal Connection
12083F-4
OE# (G#)
2
Am 2 7 X 1 2 8
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27X128
-55
J
C
XXXXX
CODE DESIGNATION Assigned by AMD TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) PACKAGE TYPE P = 28-Pin Plastic Dual In-Line Package (PD 028) J = 32-Pin Plastic Leaded Chip Carrier (PL 032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am27X128 128 Kilobit (16 K x 8-Bit) CMOS ExpressROM Device
Valid Combinations AM27X128-55 AM27X128-70 AM27X128-90 AM27X128-120 AM27X128-150 AM27X128-200 AM27X128-255 VCC = 5.0 V ± 5% PC, JC, PI, JI
Valid Combinations Valid Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am27X128
3
FUNCTIONAL DESCRIPTION Read Mode
To obtain data at the device outputs, Chip Enable (CE#) and Output Enable (OE#) must be driven low. CE# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be s t a bl e for at least t AC C t O E. Refer to the Switching Wavefor ms section for the timing diagram.
CE# should be decoded and used as the primary device-selecting function, while OE# be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memor y device.
Standby Mode
The device enters the CMOS standby mode when CE# is at VCC ± 0.3 V. Maximum VCC current is reduced to 1 0 0 µA. The device enters the TTL-standby mode when CE# is at VIH. Maximum VCC current is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input.
System Applications
Dur ing the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 µF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on ExpressROM device arrays, a 4.7 µF bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array.
Output OR-Tieing
To accommodate multiple memory connections, a two-line control function provides: s Low memory power dissipation, and s Assurance that output bus contention will not occur.
MODE SELECT TABLE
Mode Read Output Disable Standby (TTL) Standby (CMOS) CE# VIL X VIH VCC ± 0.3 V OE# VIL VIH X X PGM# X X X X V PP X X X X Outputs DOUT High Z High Z High Z
Note: X = Either VIH or VIL.
4
Am 2 7 X 1 2 8
ABSOLUTE MAXIMUM RATINGS
Storage Temperature OTP Products. . . . . . . . . . . . . . . . . . 65°C to +125°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . 55°C to +125°C Voltage with Respect to VSS All pins except VCC . . . . . . . . . 0.6 V to VCC + 0.6 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . 0.6 V to 7.0 V
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .40°C to +85°C Supply Read Voltages VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
N ot e :
1. Minimum DC voltage on input or I/O pins 0.5 V. During voltage transitions, the input may overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20ns. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability.
Am27X128
5
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