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Part: AM27C4096-100PC
Category:
Memory
-> EPROM
-> 8 Mb
Description: 4 Megabit ( 256 K X 16-bit ) CMOS EPROM
Company: Advanced Micro Devices, Inc.
Datasheet: Download AM27C4096-100PC datasheet File size : 679 kB
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Datasheet text preview:
FINAL
Am27C4096
4 Megabit (256 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s Fast access time -- Speed options as fast as 90 ns s Low power consumption -- 100 µA maximum CMOS standby current s JEDEC-approved pinout -- Plug-in upgrade of 1 Mbit and 2 Mbit EPROMs -- 40-pin DIP/PDIP -- 44-pin PLCC s Single +5 V power supply s ±10% power supply tolerance standard s 100% Flashrite programming -- Typical programming time of 32 seconds s Latch-up protected to 100 mA from 1 V to VCC + 1 V s High noise immunity
GENERAL DESCRIPTION
The Am27C4096 is a 4 Mbit, ultraviolet erasable programmable read-only memory. It is organized as 256 K w o rd s, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The Am27C4096 is ideal for use in 16-bit microprocessor systems. The device is available in windowed ceramic DIP packages, and plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. A M D 's CMOS process technology provides high sp ee d , low power, and high noise immunity. Typical p ower consumption is only 125 mW in active mode, and 125 µW in standby mode. All signals are TTL levels, including programming sign a l s . Bit locations may be programmed singly, in b l o ck s , or at random. The device supports AMD's Flashr ite programming algorithm (100 µs pulses), resulting in a typical programming time of 32 seconds.
BLOCK DIAGRAM
VC C VSS VPP OE# CE#/PGM# Output Enable Chip Enable and Prog Logic Y Decoder A0A17 Address Inputs Output Buffers Data Outputs DQ0DQ15
Y Gating
X Decoder
4,194,304 Bit Cell Matrix
11408F-1
Publication# 11408 Rev: F Amendment/0 Issue Date: May 1998
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) VCC = 5.0 V ± 5% VCC = 5.0 V ± 10% 90 90 50 -95 -105 -100 100 100 50 -120 120 120 50 -150 150 150 65 -200 200 200 75 250 250 75 Am27C4096 -255
CONNECTION DIAGRAMS Top View
DI P
VPP CE# (E#)/PGM# (P#) DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 VSS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE# (G#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A17 A16
P L CC
CE# (E#)/PGM# (P#)
DQ13
DQ14
DQ15
VCC
A17
A16
A15
A14 A13 A12 A11 A10 A9 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0
DQ12 DQ11 DQ10 DQ9 DQ8 VSS NC DQ7 DQ6 DQ5 DQ4 7 8 9 10 11 12 13 14 15 16
6
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 A13 A12 A11 A10 A9 VSS NC A8 A7 A6 A5
29 17 18 19 20 21 22 23 24 25 26 27 28
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE# (G#)
11408F -2
DU (Note 2)
A4
11408F-3
Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don't use (DU) for PLCC.
PIN DESIGNATIONS
A0A17 = Address Inputs CE# (E#)/ = Chip Enable Input/ PGM#/ (P#) Program Enable Input DQ0DQ15 = Data Input/Outputs OE# (G#) VCC V PP V SS = Output Enable Input = VCC Supply Voltage = Program Voltage Input = G round
LOGIC SYMBOL
18 A0A17 16 DQ0DQ15 CE# (E#)/PGM# (P#) OE# (G#)
11408F-4
2
Am27C4096
A14
VPP
A15
DU (Note 2)
ORDERING INFORMATION UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C4096
-95
D
C
B
OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) E = Extended (55°C to +125°C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am27C4096 4 Megabit (256 K x 16-Bit) CMOS UV EPROM
Valid Combinations AM27C4096-95 VCC = 5.0 V ± 5% AM27C4096-100 AM27C4096-105 VCC = 5.0 V ± 5% AM27C4096-120 AM27C4096-150 AM27C4096-200 AM27C4096-255 VCC = 5.0 V ± 5% DC, DCB, DI, DIB DC, DCB, DE, DEB, DI, DIB DC, DCB, DI, DIB DC, DCB
Valid Combinations Valid Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am27C4096
3
ORDERING INFORMATION OTP EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following:
AM27C4096
-105
P
C
OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (40°C to +85°C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION Am27C4096 4 Megabit (256 K x 16-Bit) CMOS OTP EPROM
Valid Combinations AM27C4096-105 VCC = 5.0 V ± 5% AM27C4096-120 AM27C4096-150 AM27C4096-200 AM27C4096-255 VCC = 5.0 V ± 5% PC, PI, JC, JI PC, JC
Valid Combinations Valid Combinations list configurations planned to be suppor ted in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
Am27C4096
FUNCTIONAL DESCRIPTION Device Erasure
In order to clear all locations of their programmed contents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase the device. This dosage can be obtained by exposure to an ultraviolet lamp--wavelength of 2537 Å--with intensity of 12,000 µW/cm2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be removed from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 Å, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, exp o s u r e to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance.
CE#/PGM# input inhibits the other devices from being programmed.
Program Verify
A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# at VIL, CE#/ PGM# at VIH, and VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0 DQ7. This mode is primarily intended for programming equipment to automatically match a device to be program me d with its corresponding programming algor i t h m . This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device. To activate this mode, the programming equipment must force VH on address line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at VIL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit.
Device Programming
Upon delivery, or after each erasure, the device has all of its bits in the "ONE", or HIGH state. "ZEROs" are loaded into the device through the programming proc e d u re . The device enters the programming mode when 12.75 V ± 0.25 V is applied to the VPP pin, and CE#/PGM# is at VIL and OE# is at VIH. For programming, the data to be programmed is applied 16 bits in parallel to the data pins. The flowchart in the Programming section (Section 5, F i g u r e 5-1) shows AMD's Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 µs programming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while sequencing through each address of the device. This part of the algorithm is done at VCC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at VCC = VPP = 5.25 V. Please refer to Section 5 for additional programming infor mation and specifications.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#/ PGM#) and Output Enable (OE#) must be driven low. CE#/PGM# controls the power to the device and is typically used to select the device. OE# enables the device to output data, independent of device selection. Addresses must be stable for at least tACCtOE. Refer to th e Switching Waveforms section for the timing diagram.
Standby Mode
T h e device enters the CMOS standby mode when CE#/PGM# is at VCC ± 0.3 V. Maximum VCC current is reduced to 100 µA. The device enters the TTL-standby mode when CE#/PGM# is at VIH. Maximum VCC curr e n t is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-impedance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a two-line control function provides: s low memory power dissipation, and s assurance that output bus contention will not occur. CE#/PGM# should be decoded and used as the primary device-selecting function, while OE# be made a
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for CE#/PGM#, all l i ke inputs of the devices may be common. A TTL low-level program pulse applied to one device's CE#/ P G M # input with VPP = 12.75 V ± 0.25 V and OE# HIGH will program that particular device. A high-level
Am27C4096
5
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