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Part: ALD500SC
Category:
Description: Precision Integrating Analog Processor
Company: Advanced Linear Devices
Datasheet: Download ALD500SC datasheet File size : 445 kB
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ADVANCED LINEAR DEVICES, INC.
ALD500AU/ALD500A/ALD500 PRECISION INTEGRATING ANALOG PROCESSOR
APPLICATIONS · · · · · · · 4 1/2 digits to 5 1/2 digits plus sign measurements Precision analog signal processor Precision sensor interface High accuracy DC measurement functions Portable battery operated instruments Computer peripheral PCMCIA
BENEFITS · · · · Wide dynamic signal range Very high noise immunity Low cost, simple functionality Automatic compensation and cancellation of error sources · Easy to use to acquire true 18 bit,17 bit, or 16 bit conversion and noise performance · Inherently linear and stable with temperature and component variations FEATURES · Resolution up to 18 bits plus sign bit and over-range bit · Accuracy independent of input source impedances · High input impedance of 1012 · Inherently filters and integrates any external noise spikes · Differential analog input · Wide bipolar analog input voltage range ±3.5V · Automatic zero offset compensation · Low linearity error - as low as 0.002% · Fast zero-crossing comparator - 1µs · Low power dissipation - 6mW typical · Automatic internal polarity detection · Low input current - 2pA typical · Microprocessor controlled conversion · Optional digital control from a microcontroller, an ASIC, or a dedicated digital circuit · Flexible conversion speed versus resolution trade-off PIN CONFIGURATION
ALD500 CINT VCAZ BUF AGND C-REF C+REF V-REF 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V+ DGND COUT B A V+IN V-IN V+REF
GENERAL DESCRIPTION The ALD500AU/ALD500A/ALD500 are integrating dual slope analog processors, designed to operate on ±5V power supplies for building precision analog-to-digital converters. The ALD500AU/ALD500A/ ALD500 feature specifications suitable for 18 bit/17 bit/16 bit resolution conversion, respectively. Together with three capacitors, one resistor, a precision voltage reference, and a digital controller, a precision Analog to Digital converter with auto zero can be implemented. The digital controller can be implemented by an external microcontroller, under either hardware (fixed logic) or software control. For ultra high resolution applications, up to 23 bit conversion can be implemented with an appropriate digital controller and software. The ALD500 series of analog processors accept differential inputs and the external digital controller first counts the number of pulses at a fixed clock rate that a capacitor requires to integrate against an unknown analog input voltage, then counts the number of pulses required to deintegrate the capacitor against a known reference voltage. This unknown analog voltage can then be converted by the microcontroller to a digital word, which is translated into a high resolution number, representing an accurate reading. This reading, when ratioed against the reference voltage, yields an accurate, absolute voltage measurement reading. The ALD500 analog processors consist of on-chip digital control circuitry to accept control inputs, integrating buffer amplifiers, analog switches, and voltage comparators. It functions in four operating modes, or phases, namely auto zero, integrate, deintegrate, and integrator zero phases. At the end of a conversion, the comparator output goes from high to low when the integrator crosses zero during deintegration. ALD500 analog processors also provide direct logic interface to CMOS logic families. ORDERING INFORMATION
0° C to +70°C 16-Pin Plastic Pin Package ALD500PC (16 bit) ALD500APC (17 bit) ALD500AUPC (18 bit) Operating Temperature Range * 0° C to +70°C 0°C to +70°C 16-Pin Small Outline Package (SOIC) ALD500SC (16 bit) ALD500ASC (17 bit) ALD500AUSC (18 bit) 16-Pin Wide Body Small Outline Package (SOIC) ALD500SWC (16 bit) ALD500ASWC (17 bit) ALD500AUSWC (18 bit)
PC, SC, SWC PACKAGE
* Contact factory for industrial temperature range
Rev. 1.02 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 http://www.aldinc.com
FIGURE 1. ALD 500 Functional Block Diagram
CREF
RINT CAZ C-REF (6)
BUF
CINT
C+REF (7)
V+REF (9)
V-REF (8)
(4)
CAZ (3)
CINT (1)
SWR SWIN V+IN (11) SW-R
SWR
Buffer +
Integrator + +
Comp1
SW+R
Comp2
-
+ SW+R SW-R SWAZ Polarity Detection
Level Shift
COUT (14)
SWAz AGND (5) V-IN (10) SWIN
SWS
DGND (15)
SWG Analog Switch Control Signals Phase Decoding Logic
VSS (2)
VDD (16)
A B (12) (13) Control Logic
GENERAL THEORY OF OPERATION Dual-Slope Conversion Principles of Operation The basic principle of dual-slope integrating analog to digital converter is simple and straightforward. A capacitor, CINT, is charged with the integrator from a starting voltage, VX, for a fixed period of time at a rate determined by the value of an unknown input voltage, which is the subject of measurement. Then the capacitor is discharged at a fixed rate, based on an external reference voltage, back to VX where the discharge time, or deintegration time, is measured precisely. Both the integration time and deintegration time are measured by a digital counter controlled by a crystal oscillator. It can be demonstrated that the unknown input voltage is determined by the ratio of the deintegration time and integration time, and is directly proportional to the magnitude of the external reference voltage. The major advantages of a dual-slope converter are: a. Accuracy is not dependent on absolute values of integration time tINT and deintegration time tDINT, but is dependent on their relative ratios. Long-term clock frequency variations will not affect the accuracy. A standard crystal controlled clock running digital counters is adequate to generate very high accuracies. b. Accuracy is not dependent on the absolute values of RINT and CINT. as long as the component values do not vary through a conversion cycle, which typically lasts less than 1 second.
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c. Offset voltage values of the analog components, such as VX, are cancelled out and do not affect accuracy. d. Accuracy of the system depends mainly on the accuracy and the stability of the voltage reference value. e. Very high resolution, high accuracy measurements can be achieved simply and at very low cost. An inherent benefit of the dual slope converter system is noise immunity. The input noise spikes are integrated (averaged to near zero) during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters and other high resolution converters and perform very well in high-noise environments. The slow conversion speed of the integrating converter provides inherent noise rejection with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed. Integrating converters often establish the integration period to reject 50/60Hz line frequency interference signals. The relationship of the integrate and deintegrate (charge and discharge) of the integrating capacitor values are shown below: VINT = VX - (VIN . tINT / RINT . CINT)
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
(integrate cycle) VX = VINT - (VREF . tDINT / RINT . CINT) (deintegrate cycle) Combining equations 1 and 2 results in: VIN / VREF = -tDINT / tINT
(1)
(2)
Phase, internal analog switches connect VIN to the buffer input where it is maintained for a fixed integration time period (tINT). This fixed integration period is generally determined by a digital counter controlled by a crystal oscillator. The application of VIN causes the integrator output to depart 0V at a rate determined by VIN and a direction determined by the polarity of VIN. The Reference Voltage Deintegration Phase is initiated immediately after tINT, within 1 clock cycle. During Reference Voltage Deintegration Phase, internal analog switches connect a reference voltage having a polarity opposite that of VIN to the integrator input. Simultaneously the same digital counter controlled by the same crystal oscillator used above is used to s t a r t counting clock pulses. The Reference Voltage Deintegration Phase is maintained until the comparator output inside the dual slope analog processor changes state, indicating the integrator has returned to 0V. At that point the digital counter is stopped. The Deintegration time period (tDINT), as measured by the digital counter, is directly proportional to the magnitude of the applied input voltage. After the digital counter value has been read, the digital counter, the integrator, and the auto zero capacitor are all reset to zero through an Integrator Zero Phase and an Auto Zero Phase so that the next conversion can begin again. In practice, this process is usually automated so that analog-todigital conversion is continuously updated. The digital control is handled by a microprocessor or a dedicated logic controller. The output, in the form of a binary serial word, is read by a microprocessor or a display adapter when desired.
(3)
where: Vx = An offset voltage used as starting voltage VINT = Voltage change across CINT during tINT and during tDINT (equal in magnitude) VIN = Average, or an integrated, value of input voltage to be measured during tINT (Constant VIN ) tINT = Fixed time period over which unknown voltage is integrated tDINT = Unknown time period over which a known reference voltage is integrated VREF = Reference Voltage CINT = Integrating Capacitor value RINT = Integrating Resistor value Actual data conversion is accomplished in two phases: Input Signal Integration Phase and Reference Voltage Deintegration Phase. The integrator output is initialized to 0V prior to the start of Input Signal Integration Phase. During Input Signal Integration
CINT RINT INTEGRATOR
ANALOG INPUT (VIN) S1
+
VINT
+
COMPARATOR
COUT
-
D OLARITY P ETECTION C ONTROL L OGIC
RVOLTAGE EFERENCE
S REF WITCHES
SWITCH DRIVER
CPHASE ONTROL
POLARITY CONTROL A B
INTEGRATOR OUTPUT
VIN VFULL SCALE VIN 1/2 VFULL SCALE VX 0 tDINT tINT tDINT
VINT = 4.1V MAX MI(CROCONTROLLER CONTROL LOGIC + COUNTER)
Figure 2. Basic Dual-Slope Converter
Figure 2. Basic Dual-Slope Converter
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
3
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V+ Differential input voltage range Power dissipation Operating temperature range PC, SC, SWC package Storage temperature range Lead temperature, 10 seconds 13.2V -0.3V to V + +0.3V 600 mW 0°C to +70°C -65 °C to +150°C +260°C
OPERATING ELECTRICAL CHARACTERISTICS TA = 25°C V+ = +5.0V V- = -5.0V (VSUPPLY = ±5.0 V) unless otherwise specified; CAZ = CREF = 0.47µf
500AU Parameter Resolution Zero-Scale Error End Point Linearity Best Case Straight Line Linearity Zero-Scale Temperature Coefficient Z SE Symbol Min 15 Typ 30 0.0025 0.003 0.005 0.007 0.0025 0.004 TCZS 0.3 0.15 0.005 0.008 1.3 0.6 0.3 0.3 0.15 0.008 0.010 1.3 0.005 Max Min 30 500A Typ 60 0.003 0.005 0.010 0.015 0.005 0.008 0.7 0.35 0.3 0.15 0.01 0.012 1.3 0.005 Max Min 60 0.005 0.008 0.015 0.020 0.008 0.015 0.7 0.35 µV/°C ppm/°C % % ppm/°C 0°C to 70°C 0°C to +70°C 500 Typ Max Unit µV % % % Test Conditions Note 1
0°C to 70°C Notes 1, 2 0°C to +70°C Notes 1, 2 0°C to +70°C 0°C to +70°C Note 1
ENL
NL
0.003
0.003
%
Full-Scale SYE Symmetry Error (Rollover Error) Full-Scale Temperature Coefficient Input Current Common-Mode Voltage Range Integrator Output Swing Analog Input Signal Range Voltage Reference Range TCFS
IIN V- +1.5 V- +0.9 V- +1.5 V- +1
2 V+-1.5 V+-0.9 V+-1.5 V+-1
V- +1.5
2 V+ -1.5 V+ -0.9 V+ -1.5 V+ -1 V-+1.5 V-+0.9 V-+1.5 V-+1
2 V+ -1.5 V+ -0.9 V+ -1.5 V+ -1
pA
VIN = 0V
CMVR
V
VINT
V- +0.9
V
VIN
V- +1.5
V
AGND = 0V
VREF
V -+1
V
4
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
DC ELECTRICAL CHARACTERISTICS TA = 25°C V+ = +5.0V V- = -5.0V (VSUPPLY = ±5.0 V) unless otherwise specified; CAZ = CREF = 0.47µf
500AU Parameter Supply Current Power Dissipation Positive Supply Range Symbol IS PD V+S 4.5 Min Typ 0.6 Max 1.0 10 5.5 4.5 Min 500A Typ 0.6 Max 1.0 10 5.5 4.5 Min 500 Typ 0.6 Max 1.0 10 5.5 Unit mA mW V Test Conditions V+ = 5V , A =1,B=1 VSUPPLY = ±5V Note 4
Negative Supply Range
V-S
-4.5
-5.5
-4.5
-5.5
-4.5
-5.5
V
Note 4
Comparator Logic 1, Output High Comparator Logic 0, Output Low Logic 1, Input High Voltage Logic 0, Input Low Voltage Logic Input Current Comparator Delay
VOH
4
4
4
V
ISOURCE = 400µA
VOL
0.4
0.4
0.4
V
ISINK = 1.1mA
VIH
3.5
3.5
3.5
V
VIL
1
1
1
V
IL tD
0.01 1
0.01 1
0.01 1
µA µsec Note 5
NOTES: 1. Integrate time 66 msec., Auto Zero time 66 msec., VINT ~ 4V, VIN = 2.0V Full Scale = Resolution = VINT /integrate time/clock period 2. End point linearity at ±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment. 3. Rollover Error also depends on CINT, CREF, C AZ characteristics. 4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ±2.5V. 5. Recommended selection of clock periods of one of the following: t clk = 0.27µsec, 0.54µsec, or 1.09µsec which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.
Figure 3. ALD500 TIMING DIAGRAM
1 Conversion Cycle
123,093 Clock Pulses 1.8432 MHz Clock A INPUT 0.5416 µs 123,093 Clock Pulses
~ ~
~ ~
66.667 msec.
~ ~
~ ~
~ ~
COUT Positive Input Signal COUT Negative Input Signal
NOT VALID
NOT VALID
Auto Zero Phase
Input Signal Integration Phase
Fixed number of clock pulses by design.
Reference Voltage Deintegration Phase
Variable number of clock pulses.
Integrator Zero Phase
~ ~
B INPUT
~ ~
66.667 msec.
~ ~
~ ~
Auto Zero Phase
START CONVERSION CYCLE
Clock data in or clock data out of counters within the the microcontroller or fixed logic controller, as needed.
Fixed period of approx.1 msec.
At VIN MAX, max. number of clock pulses ~ = 246,185
Stop counter upon detection of comparator output going from high to low state.
REPEAT CONVERSION CYCLE
START INTEGRATION CYCLE START DEINTEGRATION CYCLE START INTEGRATOR ZERO CYCLE
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
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