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Part: SAA2500H
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INTEGRATED CIRCUITS
DATA SHEET
SAA2500 MPEG Audio Source Decoder
Preliminary specification File under Integrated Circuits, IC01 September 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
MPEG Audio Source Decoder
FEATURES · Advanced error protection · Integrated audio post processing for control of signal level and inter-channel crosstalk · Demultiplexing of ancillary data in the input bitstream · Automatic digital de-emphasis of the decoded audio signal · Separate master and slave inputs · Automatic sample frequency and bit-rate switching in master input mode · Automatic synchronization of input and output interface clocks in master input mode · Selectable audio output precision; 16, 18, 20 or 22 bit · Low power consumption. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA2500H Note QFP44(1) DESCRIPTION Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm APPLICATIONS
SAA2500
· Cable and satellite digital radio decoders · Video CD · Compact Disc Interactive (CD-I) · Sold-state audio · Multimedia Personal Computer (PC). GENERAL DESCRIPTION The SAA2500 supports all audio modes (joint stereo, stereo, single channel and dual channel) bit rates and sample frequencies of ISO/MPEG-1 layers I and II, as standardized in "ISO/IEC 11172-3".
VERSION SOT307-2
1. When using IR reflow soldering it is recommended that the Drypack instructions in the "Quality Reference Pocketbook" (order number 9398 510 34011) are followed. Supply of this "ISO/IEC 11172-3" audio standard Layer I or layer II compatible IC does not convey a licence nor imply a right under any patent, or any Industrial or Intellectual Property Right, to use this IC in any ready-to-use electronic product.
September 1994
2
Philips Semiconductors
Preliminary specification
MPEG Audio Source Decoder
BLOCK DIAGRAM
SAA2500
FSCLK384
MCLKOUT
FSCLKIN
MCLK24
X22OUT
L3MODE
FSCLKM
MCLKIN
FSCLK
L3DATA
L3CLK
handbook, full pagewidth
5 TDI TDO TCK TMS TRST CDS CDSEF CDSCL CDSWA CDSSY CDM CDMEF CDMCL CDMWS 41 37 39 40 38 19 20 18 21 22
34
8
7
4
44
10
9
3
2
42 43
24 25 23
11 12
URDA 1
X22IN
MCLK
V DD1 V DD2
G CLOCK ENERATOR
DECODING C ONTROL
STOP
RESET
SAA2500
DEQUANTIZ ATION A S ND P CALING ROCESSOR SS NTHESYS Y UBBAND F BLTER I A NK A O ND P UTPUT ROCESSING
P 15 14 16 13
INPUT ROCESSOR
26
SD
36 TC0
35 TC1
17 GND
28 GND
6 GND
27 33 31 32 TA TB TO TI
29
30
MGB489
SCK WS
Fig.1 Functional block diagram.
September 1994
3
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