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Part: M24C32-MN6
Category:
Description: Ic-sm-32k EePROM
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Datasheet: Download M24C32-MN6 datasheet File size : 13 kB
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M24C64 M24C32
64K/32K SERIAL I2C BUS EEPROM
PRELIMINARY DATA
COMPATIBLE with I2C EXTENDED ADDRESSING TWO WIRE I2C SERIAL INTERFACE, SUPPORTS 400kHz PROTOCOL 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE 4.5V to 5.5V for M24C64 and M24C32 2.5V to 5.5V for M24C64-W and M24C32-W 1.8V to 3.6V for M24C64-R and M24C32-R HARDWARE WRITE CONTROL BYTE and PAGE WRITE (up to 32 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD and LATCH-UP PERFORMANCES
8 1
PSDIP8 (BN) 0.25mm Frame
14 1
T SSOP14 (DL) 169mil Width
8 1
SO8 (MN) 150mil Width
8 1
SO8 (MW) 200mil Width
Figure 1. Logic Diagram
DESCRIPTION The M24C64 and the M24C32 are 64K bit and a 32K bit electrically erasable programmable memories (EEPROM), organized as 8,192 x 8 and as 4,096 x 8 bits respectively. The "-W" versions op erate with a power supply value as low as 2.5V and the "-R" versions operate down to 1.8V. Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages are available.
VCC
3 E0-E2 SCL M24C64 M24C32 SDA
Table 1 . Signal Names
E0-E2 SDA SCL WC VCC VSS Chip Enable Inputs Serial Data Address Input/Output Serial Clock Write Control Supply Voltage Ground
WC
VSS
AI01844B
February 1998
This is preliminary informatio n on a new product n ow in developm ent or undergoing evaluation . Detail s a re subject to change without notice.
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M24C64, M24C32
Table 2 . Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD Parameter Ambient Operating Temperature (2) Storage Temperature Lead Temperature, Soldering (SO8 package) (PSDIP8 package) (TSSOP14 package) 40 sec 10 sec t.b.c. Value 40 to 125 65 to 150 215 260 t.b.c. 0.6 to 6.5 0.3 to 6.5 4000 500 Unit °C °C °C V V V V
VIO VCC V ESD
Input or Output Voltages Supply Voltage Electrostatic Discharge Voltage (Human Body model) (3) Electrostatic Discharge Voltage (Machine model)
( 4)
Notes: 1. Except for the rating "Operating Temperature Range", s tresses above those lis ted in the Table "Absolute Maximum Ra tings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this s pecification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON S URE Program and other re levant quality documents. 2. Depends on range. 3. 100pF through 1500; MIL-STD-883C, 3015.7 4. 200pF through 0; EIAJ IC-121 (condition C)
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
M24C64 M24C32 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI01845B
M24C64 M24C32 VCC WC SCL SDA E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI01846B
VCC WC SCL SDA
Figure 2C. TSSOP Pin Connections
M24C64 M24C32 E0 E1 NC NC NC E2 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8
AI02129
VCC WC NC NC NC SCL SDA
DESCRIPTION (cont'd) Each memory is compatible with the I2C extended addres sing sta ndard, t wo wire se rial inte rfa ce which uses a bi-directional data bus and serial clock. The memory carries a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The memory behaves as slave devices in t he I2C protocol with all memory operations synchronized by the serial clock. Read and write operation s are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 4 bits (identification code 1010), then 3 bit Chip Enable input to form a 7 bit Device Select, plus one read/write bit and terminated by an acknowledge bit.
Warning: NC = Not Connected. 2/18
M24C64, M24C32
Table 3 . Device Select Code
D evice Code Bit Device Select
Note: The MSB b7 is sent first.
Chip Enable b4 0 b3 E2 b2 E1 b1 E0
RW b0 RW
b7 1
b6 0
b5 1
Table 4 . Operating Modes
Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write RW bit '1' '0' '1' '1' '0' '0' WC X X X X VIL VIL 1 1 32 Data Bytes 1 1 Initial Sequence START, Device Select, R W = '1' START, Device Select, R W = '0', Address, reSTART, Device Select, R W = '1' As CURRENT or RANDOM Mode START, Device Select, R W = '0' START, Device Select, R W = '0'
When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. In this way, up to 8 memories may be conn e c t e d t o t h e s a m e I2C b u s a n d s e l e c t e d individually. Power On Reset: VC C lock o ut write protect. I n order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Untill the VCC voltage has reached the POR threshold value, the internal reset is active: all operations are disabled and the device will not respond to any command. In t he same way, when VCC drops down from the operating voltage to below t he POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. SIGNALS DESCRIPTION Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connecte d from the SCL line to VCC to act as a pull up (see Figure 3)
Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A resistor must be connected from t he SDA bus line to VCC to act as pull up (see F igure 3). Chip Enable (E0-E2). These chip enable inputs are used to set the 3 least significant bits of the 7 bit device select code. They may be driven dynamically or tied to VCC or VSS to establish the device select code. Note that the VIL and VIH levels for the inputs are CMOS, not TTL compatible. Write Control (WC). T he Write Control feature WC is useful to protect the contents of the memory from any erroneous erase/write cycle. The Write Control signal is used to enable (WC a t VIH) or disable (WC at VIL) the internal write protection. When pin WC is unconnec ted, t he WC input is internally read as VIL (see Table 5). When WC = '1', Device Select and Address bytes are acknowledged; Data bytes are no t acknowledged. Refer t o the AN404 Application Note for more detailed information about Write Control feature.
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