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Part: IS24C01-I
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IS24C01
IS24C01
1024-BIT SERIAL ELECTRICALLY ERASABLE PROM
ISSI
OVERVIEW
ISSI®
®
ADVANCE INFORMATION APRIL 1998
FEATURES · Low power CMOS -- Active current less than 2 mA -- Standby current less than 8 µA · Hardware write protection -- Write control pin · Internally organized as128 x 8 · Two-wire serial interface -- Bidirectional data transfer protocol · 8-Byte page-write mode -- Minimized total write time per byte · Automatic word address incrementing -- Sequential register read · Self-timed write cycle -- Maximum write cycle time of 10 ms · 400 KHz Compatibility · Endurance: 100K cycles per byte · 8-pin PDIP or SOIC packages · Filtered inputs for noise suppression
The IS24C01 is a low cost 1,024-bit serial EEPROM. It is fabricated using ISSI's advanced CMOS EEPROM technology and operates from a single supply. The IS24C01 is internally organized as a 128 x 8 memory bank. The IS24C01 features a serial interface and software protocol allowing operation on a simple 2-wire bus. Up to eight IS24C01s may be connected to the 2-wire bus by controlling the A0, A1, and A2 inputs.
FUNCTIONAL BLOCK DIAGRAM
Vcc
8
HIGH VOLTAGE GENERATOR, TIMING AND CONTROL
SDA SCL WC
5
X DECODER
6 7
CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR
Load Inc.
32
32 x 32 MEMORY CORE
A2 A1 A0
3 2 1
WORD ADDRESS COUNTER
32
Y DECODER
GND
4
ACK
Clock DI/O
nMOS
DATA REGISTER
This document contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE014-0A 04/16/98
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IS24C01
PIN CONFIGURATION 8-Pin DIP and SOIC PIN DESCRIPTIONS
A0-A2 SDA
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WC SCL SDA
ISSI
Address Inputs Serial Data I/O Serial Clock Input Write Control Input Power Ground
®
SCL
WC
Vcc GND
PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock all data into and out of the device. In the WRITE mode, data must remain stable when SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW. It is an open-drain output, and may be wire-ORed with any number of open-drain or open-collector outputs. A0, A1, and A2 - The address inputs are used to set the three least significant bits of the slave address. These inputs may be tied HIGH or LOW, or they may be actively driven. These inputs allow up to eight IS24C01 devices to be connected together on the bus. Write Control (WC) - The Write Control input is used to WC disable any attempt to write to the memory. When HIGH, the memory is protected; when LOW, the write function is normal. The part can be read independent of the state of WC pin. When not connected this pin will be pulled LOW.
GENERAL DESCRIPTION
The IS24C01 features a SERIAL communication, and supports bidirectional data transmission protocol allowing operation on a simple two-wire bus between the different devices connected somewhere to the system bus. The two-wire bus is defined as a serial data line (SDA), and a serial clock line (SCL). (Refer to Figure 1. Typical System Bus Configuration.) The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving device as a receiver. The device controlling the data transmission is named MASTER device, and the controlled device is named SLAVE device. In all cases, the IS24C01 will be a slave device, since it never initiates any data transfers. Up to eight IS24C01 can be connected to the bus. Device's physical address inputs A0-A2 must be connected to either Vcc or GND, or driven to logic HIGH or LOW state. Following a START condition, the MASTER (transmitter) device must initiate the "Device Addressing Byte" including device type identifier, device address, and a read or write operation to select a slave device (receiver) connected to the system bus. The receiver will then respond with an ACKnowledge by pulling the SDA line LOW. The ACKnowledge is used to indicate successful data transfers. The transmitting device will release the data bus (SDA goes HIGH) after transmitting eight bits (one data bit is transfered at the falling edge of each clock cycle). During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge the reception of the eight bits of data. (Refer to Figure 2. ACKnowledge Response from Receiver Diagram.)
ENDURANCE AND DATA RETENTION
The IS24C01 is designed for applications requiring highendurance write cycles and unlimited read cycles. It provides 10 years of secure data retention, with or without power applied, after the execution of 100K write cycles.
APPLICATIONS
The IS24C01 is ideal for high volume applications requiring low power and low density storage. This device uses a lowcost, space-saving 8-pin plastic package. Candidate applications include robotics, alarm devices, electronic locks, meters and instrumentation.
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Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE014-0A 04/16/98
IS24C01
DEVICE OPERATION
START and STOP Conditions Both SDA and SCL lines remain HIGH when the SDA bus is not busy. A HIGH-to-LOW transition of SDA line, while SCL is HIGH, is defined as the START condition. A LOWto-High transition of SDA line, while SCL is HIGH, is defined as the STOP condition. (Refer to Figure 3. Start and Stop Conditions.) Data Validity Protocol One data bit is transferred during each clock cycle. The data on the SDA line must remain stable during the HIGH period of the clock cycle, because changes on SDA line during the SCL HIGH period will be interpreted as START or STOP control signals. (Refer to Figure 4. Data Validity Protocol.) Device Addressing Byte Definitions The four most significant bits of Device Addressing Byte (Bit 7 to Bit 4) are defined as the device type identifier. For IS24C01, this is fixed as 1010. The next three address bits (Bit 3 to Bit 1) address a particular device. Up to eight IS24C01 devices can be connected to the same bus. These eight addresses are defined by the state of the A0, A1, and A2 inputs. Bit 0 defines the write or read operation to be performed. When set to "1", a READ operation is selected; when set to "0" a WRITE operation is selected. (Refer to Figure 5. Device Addressing Byte Definitions.)
ISSI
®
Page Write The IS24C01 is capable of 8-byte page- WRITE operation. A page-WRITE is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the first data word is transfered, the master device can transmit up to seven more words. After the receipt of each data word, the IS24C01 responds immediately with an ACKnowledge on SDA line, and the three lower order data word address bits are internally incremented by one while the higher order bits of the data word address remain constant. If the master device should transmit more than eight words, prior to issuing the STOP condition, the address counter will "roll over," and the previously written data will be overwritten. All inputs are disabled until completion of the internal WRITE cycle. (Refer to Figure 6. Write Operation for the Address, ACKnowledge, and Data Transfer Sequence.) Acknowledge Polling Once the internal write cycle has started and the IS24C01 inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the Device Addressing Byte. The read/write bit is representive of the operation desired. Only if the internal write cycle has been completed will the IS24C01 respond with an acknowledge on the SDA bus allowing the read or write sequence to continue.
READ OPERATION WRITE OPERATION
Byte Write For a WRITE operation, the IS24C01 requires another 8-bit data word address following the Device Addressing Byte and ACKnowledgement. This data word address provides access to any one of the 128 data words of device's memory array. Upon receipt of the data word address, the IS24C01 responds with an ACKnowledge on SDA, and waits for the next 8-bit data word, then again responding with an ACKnowledge. The master device terminates the Byte Write Operation by generating a STOP condition, afterward the IS24C01 begins the internal WRITE cycle to the nonvolatile memory array. Refer to Write Cycle Timing. All inputs are disabled during this write cycle and the device will not response to any requests from the master. (Refer to Figure 6. Write Operation for the Address, ACKnowledge, and Data Transfer Sequence.) READ operations are initiated in the same manner as WRITE operations, except that the read/write bit of the device addressing byte is set to "1". There are three READ operation options: current address read, random address read and sequential read. Current Address Read The IS24C01 contains an internal address counter which maintains the address of the last data word accessed, incremented by one. For example, if the previous operation, either a read or write operation, addressed the location n, the internal address counter would be n+1. When the IS24C01 receives the Device Addressing Byte with a READ operation (read/write bit set to "1"), it will respond with an ACKnowledge and transmit the 8-bit data word stored at address location n+1. If the Current Address READ operation only accesses a single byte of data, the master device terminates the Current Address READ o p e r a t i o n by pulling ACKnowledge HIGH (no ACKnowledge) indicating the last data word to be read, followed by a STOP condition. (Refer to Figure 7. Current Address Read Diagram.)
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE014-0A 04/16/98
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