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Part: 0RTC72423B
Category:
Description: Ic-sm-real Time Clock
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Datasheet: Download 0RTC72423B datasheet File size : 185 kB
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R e a l Time Clock Modules - Seiko Epson
RTC-72421/72423 Features
· Built-in quartz crystal makes regulation unnecessary and allows for easy design · ALE INPUT terminal available for 8048, 8051 and 8085 series · Incorporates built-in time counters (year, month, week, day) · 12hr/24hr clock switchcover function and automatic leap year setting · 30 seconds error adjustment function · READ, WRITE, HOLD, STOP, RESET and CHIP SELECT inputs · The CMOS IC boasts low current consumption & features a backup function · 18 pin dual-in-line package · Pin and function are compatible with the SMC 5242C
Absolute Max. Rating
Item Supply voltage Input and Output voltage Storage temp. Symbol VDD VI/O TSTG Condition Ta=25°C Ta=25°C RTC-72421 RTC-72423 RTC-72421 RTC-72423 Specification -0.3 ~ +7.0 GND -0.3 ~ VDD +0.3 -55 ~+85 -55 ~ +125
Under 260°C within 10S (lead part) (package should be less than 150°C) Under 260°C within 10S x 2 time under 230°C withhin 3 min
Unit V V °C
Terminal Connection
Soldering condition
TSOL
Operating Voltage
Item Operating voltage Operating temperature Data holding voltage CSI data holding time Operating restoring time Symbol VDD TOPR VDH tCDR tR Condition Refer to the data holding timing
Specification 4.5 ~ 5.5 -40 ~ +85 2.0 ~ 5.5 2.0 min.
Unit V °C V µS
Frequency and Current Consumption Characteristics
Item Symbol Condition 72421A Ta=25°C 72421B V =5V 72423A 7243B -10 ~ +70°C,
DD
Specification Unit ±10 ±50 ±20 ±50 ±10/-120
Frequency tolerance Frequency temperature characteristics Aging Shock resistance Current consumption
f/fo
ppm ppm
(25°C reference temperature)
Dimensions (mm)
fa S.R. IDD1 IDD2
VDD=5V, Ta25°C, 1st year Drop test of 3 times on a hard board from 75cmheight of 300G x 0.3mS x 1/2 sine wave x 3 directions
±5 max. ±5 max. 10 max. 5 Max.
ppm ppm µA µA
CSIov
VDD=5V VDD=2V
Electrical Characteristics
Item "H" Input Voltage (1) "L" Input Voltage (1) Input leakage current (1) Input leakage current (2) "L" output voltage (1) "H" output voltage "L" output voltage (2) OFF leak current Input capacity "H" Input Voltage (2) "L" Input Voltage (2) Symbol Condition VIH1 VIHL IIK1 ILK2 VOL1 VOH VOL2 IOFFLK C1 VIH2 VIH2 V1=VDD/0V IOL=2.5mA IOH=-400µA IOL=2.5mA V1=VDD/0V
Input Frequency 1MHz
Min 2.2 -
Typ. 5 -
Max. Unit 0.8 1/-1 10/-10 0.4 0.4 10 1/5VDD V µA
Applicable terminal
All inputs other than CSI
Input other than D2 ~ D3 D0 ~ D3
2.4 -
V V µA pF V
D0 ~ D3
STD.P
VDD=2~5.5V 4/5VDD -
CSI1
T E L : + 4 4 1 6 3 5 5 2 8 5 2 0 FA X : + 4 4 1 6 3 5 5 2 8 4 4 3
Real Time Clock Modules - Seiko Epson
RTC-72421/72423 Continued Notes
0="L" revel, 1="H" revel, REST=RESET ITRPT/STND=INTRUPT/STANDARD 1. Bit * does not exist 2. Please mask AM/PM bit with 10's of hours operation 3. Busy is read only. IRQ can only be set low ("0") 4. Data Bit 1 0 PM/AM PM AM ITRPT/STND ITRPT STND 24/12 24 12 6 7 8 9 A B C D E F 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 d8 0 D1 * 1 D10 0 M01 mo8 1 M010 * y8 0 Y1 1 Y10 y80 0W * 1 Reg D 30 sec
ADJ
Function Table
Address Register
A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0
D3 S8 * mi8 * h8 *
D2 S4 S40 mi4 mi40 h4
PM/AM
Data Count D1 D0 value S2 S20 mi2 mi20 h2 h20 S1 S10 mi1 mi10 h1 h10 0~9 0~5 0~9 0~5 0~9 0~2 0~1 0~9 0~3 0~9 0~1 0~9 0~9 0~6 or
Remarks 1 second digit register 10 second digit register 1 minute digit register 10 minute digit register 1 hour digit register
PM/AM, 10 hour digit register
0 1 2 3 4 5
0 S1 1 S10 0 MI1 1 MI10 0 H1 1 H1
Write Mode (with ALE)
d4 * mo4 * y4 y40 w4
IRQ FLAG t0
d2 d1 d20 d10 mo2 mo1 * mo10 y2 y1 y20 y10 w1 w2
BUSY HOLD
1 day digit register 10 day digit register 1 month digit register 10 month digit register 1 year digit register 10 year digit register week register Control register D Control register E Control register F
0 1
Reg E
t1
ITRPT /STND
MASK
Reg F
TEST
24/12
STOP
REST
Read Mode (with ALE)
Switching Characteristics (with ALE)
Please connect ALE to VDD (If the microprocessor does not have an ALE OUTPUT)
Item CS1 set up time Address set up time Address hold time ALE pulse width ALE before WRITE ALE before READ ALE before WRITE ALE before READ WHITE pulse width RD to DATA DATA hold DATA setup time DATA hold time CS1 hold time RD/WR recovery time
(VDD=5V±, Ta=-10µ70°C)
Symbol tSU(CS1) tsu(A-ALE) th(ALE-A) tW(ALE) tSU(ALE-W) tSU(ALE-R) tSU(W-ALE) tSU(R-ALE) tw/(w) tPZV(R-Q) tPVZ(R-Q) tSU(D-W) th(W-D) th(CSI) tREC(R-W)
Condition CL=150pF -
Min 1000 50 50 80 0 0 50 50 120 0 80 10 1000 200
Max 120 -
Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
Data Holding Timing
Block Diagram
1997/98 FREQUENCY CONTROL MANUAL
Others parts begin by 0r
0R-1
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